MELOPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank

• Published in: 2021 58th ACM/IEEE Design Automation Conference (DAC) pp. 601 - 606
• Main Authors: Li, Lixiang, Chen, Yao, Zirnheld, Zacharie, Li, Pan, Hao, Cong
• Format: Conference Proceeding
• Language: English
• Published: IEEE 05.12.2021
• Subjects: Hardware; Memory management; Real-time systems; Social networking (online); Throughput; Time factors; User experience
• DOI: 10.1109/DAC18074.2021.9586129

Personalized PageRank (PPR) is a graph algorithm that evaluates the importance of the surrounding nodes from a source node. Widely used in social network related applications such as recommender systems, PPR requires real-time responses (latency) for a better user experience. Existing works either focus on algorithmic optimization for improving precision while neglecting hardware implementations or focus on distributed global graph processing on large-scale systems for improving throughput rather than response time. Optimizing low-latency local PPR algorithm with a tight memory budget on edge devices remains unexplored. In this work, we propose a memory-efficient, low-latency PPR solution, namely MeLoPPR, with largely reduced memory requirement and a flexible trade-off between latency and precision. MeLoPPR is composed of stage decomposition and linear decomposition and exploits the node score sparsity: Through stage and linear decomposition, MeLoPPR breaks the computation on a large graph into a set of smaller sub-graphs, that significantly saves the computation memory; Through sparsity exploitation, MeLoPPR selectively chooses the sub-graphs that contribute the most to the precision to reduce the required computation. In addition, through software/hardware co-design, we propose a hardware implementation on a hybrid CPU and FPGA accelerating platform, that further speeds up the sub-graph computation. We evaluate the proposed MeLoPPR on memory-constrained devices including a personal laptop and Xilinx Kintex-7 KC705 FPGA using six real-world graphs. First, MeLoPPR demonstrates significant memory saving by 1. 5 \times \sim 13. 4 \times on CPU and 73 \times \sim 8699 \times on FPGA. Second, MeLoPPR allows flexible trade-offs between precision and execution time: when the precision is 80%, the speedup on CPU is up to 15\times and up to 707\times on FPGA; when the precision is around 90%, the speedup is up to 70\times on FPGA.