Hybrid LUT and SOP Reconfigurable Architecture

• Published in: Journal of Information Science and Engineering Vol. 30; no. 1; pp. 65 - 84
• Main Authors: 許博揚(Po-Yang Hsu), 陳勇志(Yung-Chih Chen), 劉一宇(Yi-Yu Liu)
• Format: Journal Article
• Language: English
• Published: Taipei 社團法人中華民國計算語言學學會 01.01.2014; Institute of Information Science, Academia sinica
• Subjects: Applied sciences; Architecture; Circuit design; Counting; Electronics; Exact sciences and technology; Field programmable gate arrays; Integrated circuits; Integrated circuits by function (including memories and processors); Phase transformations; Programmable logic devices; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors; logic synthesis; technology mapping; logic diversity analysis; timing optimization; hybrid FPGA; Circuit design; Duplication; Logic synthesis; Transistor; Field programmable gate array; Hybrid logic; Timed system; Optimization; Look up table; Delay circuit; Phase transformation; Experimental result; Programmable logic array; Advanced technology; Reconfigurable architectures
• ISSN: 1016-2364
• DOI: 10.6688/JISE.2014.30.1.4

With the increasing non-recurring engineering cost of advanced process technologies, reconfigurable devices have received great attention in small and medium-volume integrated circuit designs. However, low logic diversity and slow timing performance limit the efficacy of field-programmable gate array (FPGA) and complex programmable logic device (CPLD). In this paper, we propose an efficient hybrid lookup table (LUT)/sum-of-product (SOP) reconfigurable design style that exploits the advantages of circuit designs for both LUT cells and SOP cells. Then, architectural evaluations are performed to achieve the best cell ratio. Based on this architecture, we propose an efficient methodology for hybrid LUT/SOP logic synthesis that employs SOP-cell transformation, phase flipping, and phase duplication. The experimental results demonstrate that our proposed hybrid LUT/SOP design style achieves 35% circuit performance improvement and 52% transistor count reduction compared to the depth optimal 4-LUT-based FPGA. In comparison with the CPLD, our hybrid design style requires only 11% of the transistor count and reduces circuit delay by 11%.