Architectural synthesis of performance-driven multipliers with accumulator interleaving

VLSI multipliers assume different characteristics in terms of latency, throughput and area for different target applications. This paper proposes a methodology of automatically generating a multiplier from the user's specifications of latency, throughput, and area. The entire gamut of multiplie...

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Bibliographic Details
Published in30th ACM/IEEE Design Automation Conference pp. 303 - 307
Main Authors Ghosh, Debabrata, Nandy, S. K., Sadayappan, P., Parthasarathy, K.
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 01.07.1993
SeriesACM Conferences
Subjects
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ISBN9780897915779
0897915771
ISSN0738-100X
DOI10.1145/157485.164902

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Summary:VLSI multipliers assume different characteristics in terms of latency, throughput and area for different target applications. This paper proposes a methodology of automatically generating a multiplier from the user's specifications of latency, throughput, and area. The entire gamut of multipliers, starting from low area, moderate performance multipliers to high performance ones with low latency and/or very high throughput is captured in this synthesis procedure. The architecture comprises of a smaller core, a Front End Server (FES) and a Back End Processor (BEP) which allows to use the basic core repetitively for multiplication of larger numbers. Through a novel method of accumulator interleaving the multipliers designed using the proposed methodology support better performance compared to conventional approaches. The proposed methodology can be used for synthesis of multipliers occupying any place (feasible in a given technology) in the A - L - T (Area, Latency, Throughput) space, subject to an affordable power dissipation.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
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ISBN:9780897915779
0897915771
ISSN:0738-100X
DOI:10.1145/157485.164902