Embedded system synthesis under memory constraints

This paper presents a genetic algorithm to solve the system synthesis problem of mapping a time constrained single-rate system specification onto a given heterogeneous architecture which may contain irregular interconnection structures. The synthesis is performed under memory constraints, that is, t...

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Bibliographic Details
Published inHardware/Software Codesign 1999: Proceedings of the IEEE 7th International Conference pp. 188 - 192
Main Authors Madsen, Jan, Bjørn-Jørgensen, Peter
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 01.03.1999
IEEE
SeriesACM Conferences
Subjects
Bandwidth
Embedded computing
Embedded system
Genetic algorithms
Hardware
Information technology
Memory management
Microprocessors
Processor scheduling
Software and its engineering > Software creation and management > Designing software
Software and its engineering > Software organization and properties > Contextual software domains > Operating systems
Time factors
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ISBN9781581131321
1581131321
ISSN1092-6100
DOI10.1145/301177.301526

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Summary:This paper presents a genetic algorithm to solve the system synthesis problem of mapping a time constrained single-rate system specification onto a given heterogeneous architecture which may contain irregular interconnection structures. The synthesis is performed under memory constraints, that is, the algorithm takes into account the memory size of processors and the size of interface buffers of communication links, and in particular the complicated interplay of these. The presented algorithm is implemented as part of the LY-COS cosynthesis system.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9781581131321
1581131321
ISSN:1092-6100
DOI:10.1145/301177.301526