Statistical reliability analysis under process variation and aging effects

• Published in: 2009 46th ACM/IEEE Design Automation Conference pp. 514 - 519
• Main Authors: Lu, Yinghai, Shang, Li, Zhou, Hai, Zhu, Hengliang, Yang, Fan, Zeng, Xuan
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 26.07.2009; IEEE
• Series: ACM Conferences
• Subjects: Aging; Applied computing > Physical sciences and engineering > Engineering; Circuit analysis; Circuit optimization; Degradation; Hardware > Hardware test; Hardware > Robustness; Integrated circuit reliability; NBTI; Negative bias temperature instability; Process variations; Runtime; Statistical analysis; Threshold voltage; Timing; Yield; NBTI; process variations; yield
• ISBN: 9781605584973; 1605584975
• ISSN: 0738-100X
• DOI: 10.1145/1629911.1630044

Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance and reliability. Various aging effects, such as negative bias temperature instability, cause continuous performance and reliability degradation during circuit run-time usage. In this work, we present a statistical analysis framework that characterizes the lifetime reliability of nanometer-scale integrated circuits by jointly considering the impact of fabrication-induced process variation and run-time aging effects. More specifically, our work focuses on characterizing circuit threshold voltage lifetime variation and its impact on circuit timing due to process variation and the negative bias temperature instability effect, a primary aging effect in nanometer-scale integrated circuits. The proposed work is capable of characterizing the overall circuit lifetime reliability, as well as efficiently quantifying the vulnerabilities of individual circuit elements. This analysis framework has been carefully validated and integrated into an iterative design flow for circuit lifetime reliability analysis and optimization.