Energy-aware error control coding for Flash memories

• Published in: 2009 46th ACM/IEEE Design Automation Conference pp. 658 - 663
• Main Authors: Papirla, Veera, Chakrabarti, Chaitali
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 26.07.2009; IEEE
• Series: ACM Conferences
• Subjects: Algorithm design and analysis; Computer systems organization > Dependable and fault-tolerant systems and networks; Costs; Delay; Embedded system; Endurance; Error Control Coding; Error correction; Error correction codes; Flash memories; Flash memory; General and reference > Cross-computing tools and techniques > Performance; Hardware > Integrated circuits > Semiconductor memory; Low-power design; Networks > Network performance evaluation; Permission; Read-write memory; Writing; error control coding; low-power design; endurance; Flash memories
• ISBN: 9781605584973; 1605584975
• ISSN: 0738-100X
• DOI: 10.1145/1629911.1630085

The use of Flash memories in portable embedded systems is ever increasing. This is because of the multi-level storage capability that makes them excellent candidates for high density memory devices. However, cost of writing or programming Flash memories is an order of magnitude higher than traditional memories. In this paper, we design an algorithm to reduce both average write energy and latency in Flash memories. We achieve this by reducing the number of expensive '01' and '10' bit-patterns during error control coding. We show that the algorithm does not change the error correction capability and moreover improves endurance. Simulations results on representative bit-stream traces show that the use of the proposed algorithm saves, on average, 33% of write energy and 31% of latency of Intel MLC NOR Flash memory, and improves the endurance by 24%.