A methodology for energy-quality tradeoff using imprecise hardware

• Published in: DAC Design Automation Conference 2012 pp. 504 - 509
• Main Authors: Huang, Jiawei, Lach, John, Robins, Gabriel
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 03.06.2012; IEEE
• Series: ACM Conferences
• Subjects: Adders; Delay; energy-quality tradeoff; Error analysis; Imprecise hardware; Kernel; Mathematics of computing > Mathematical analysis > Mathematical optimization; static error estimation; Support vector machines; Theory of computation > Design and analysis of algorithms > Mathematical optimization; Vectors; energy-quality tradeoff; static error estimation; imprecise hardware
• ISBN: 1450311997; 9781450311991
• ISSN: 0738-100X
• DOI: 10.1145/2228360.2228450

Recent studies have demonstrated the potential for reducing energy consumption in integrated circuits by allowing errors during computation. While most proposed techniques for achieving this rely on voltage overscaling (VOS), this paper shows that Imprecise Hardware (IHW) with design-time structural parameters can achieve orthogonal energy-quality tradeoffs. Two IHW adders are improved and two IHW multipliers are introduced in this paper. In addition, a simulation-free error estimation technique is proposed to rapidly and accurately estimate the impact of IHW on output quality. Finally, a quality-aware energy minimization methodology is presented. To validate this methodology, experiments are conducted on two computational kernels: DOT-PRODUCT and L2-NORM -- used in three applications -- Leukocyte Tracker, SVM classification and K-means clustering. Results show that the Hellinger distance between estimated and simulated error distribution is within 0.05 and that the methodology enables designers to explore energy-quality tradeoffs with significant reduction in simulation complexity.