Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness

• Published in: 2008 45th ACM/IEEE Design Automation Conference pp. 900 - 905
• Main Authors: Ye, Yun, Liu, Frank, Nassif, Sani, Cao, Yu
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 08.06.2008; IEEE
• Series: ACM Conferences
• Subjects: Analytical models; Atomistic Simulations; Circuit analysis computing; Circuit simulation; Circuit synthesis; Computational modeling; Fluctuations; Hardware > Electronic design automation > Physical design (EDA); Hardware > Hardware validation; Line-Edge Roughness; Non-Rectangular Gate; Predictive Modeling; Predictive models; Random Dopant Fluctuations; Semiconductor process modeling; SPICE; SPICE Simulation; Threshold Variation; Threshold voltage; non-rectangular gate; predictive modeling; SPICE simulation; threshold variation; atomistic simulations; random dopant fluctuations; line-edge roughness
• ISBN: 1605581151; 9781605581156
• ISSN: 0738-100X
• DOI: 10.1145/1391469.1391698

The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations that are too expensive computationally for statistical circuit design. In this work, we develop an efficient SPICE simulation method and statistical transistor model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by sub-wavelength lithography and gate etching process. By understanding the physical principles of atomistic simulations, we (a) identify the appropriate method to divide a non-uniform gate into slices in order to map those fluctuations into the device model; (b) extract the variation of Vth from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to Vth and (c) propose a compact model of Vth variation that is scalable with gate size and the amount of dopant and gate length fluctuations. The proposed SPICE simulation method is fully validated against atomistic simulation results. Given the post-lithography gate geometry, this approach correctly models the variation of device output current in all operating regions. Based on the new results, we further project the amount of Vth variation at advanced technology nodes, to help shed light on the challenges of future robust circuit design.