Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations

• Published in: Proceedings of the Conference on Design, Automation and Test in Europe pp. 1591 - 1596
• Main Authors: Li, Min, Davoodi, Azadeh, Xie, Lin
• Format: Conference Proceeding
• Language: English
• Published: San Jose, CA, USA EDA Consortium 12.03.2012
• Series: ACM Conferences
• Subjects: Applied computing > Physical sciences and engineering > Electronics; Hardware > Hardware validation
• ISBN: 3981080181; 9783981080186
• DOI: 10.5555/2492708.2493095

This work offers a framework for predicting the delays of individual design paths at the post-silicon stage which is applicable to post-silicon validation and delay characterization. The prediction challenge is mainly due to limited access for direct delay measurement on the design paths after fabrication, combined with the high degree of variability in the process and environmental factors. Our framework is based on using on-chip delay sensors to improve timing prediction. Given a placed netlist at the pre-silicon stage, an optimization procedure is described which automatically generates the sensors subject to an area budget and available whitespace on the layout, in the presence of process variations. Each sensor is then generated as a sequence of logic gates with an approximate location on the layout at the pre-silicon stage. The on-chip sensor delay is then measured to predict the delays of individual design paths with less pessimism. In our experiments, we show that custom on-chip sensors can significantly increase the rate of predicting if a specified set of paths are failing their timing requirements.