On accelerating pattern matching for technology mapping

• Published in: Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design pp. 118 - 122
• Main Author: Matsunaga, Yusuke
• Format: Conference Proceeding Journal Article
• Language: English
• Published: New York, NY, USA ACM 1998; IEEE
• Series: ACM Conferences
• Subjects: Acceleration; Hardware > Robustness; Inverters; Laboratories; Libraries; Logic functions; Mathematics of computing > Mathematical software; Pattern matching; Permission; Theory of computation > Design and analysis of algorithms > Data structures design and analysis > Pattern matching
• ISBN: 1581130082; 9781581130089
• ISSN: 1092-3152
• DOI: 10.1145/288548.288587

The pattern matching algorithm is simple and fast compared to other such matching algorithms such as Boolean matching. One major drawback of the pattern matching is that there is a case where a cell needs a lot of patterns representing its logic function. That is because patterns are decomposed into 2-AND/NOT patterns to match against decomposed subject graphs. Furthermore, the conventional technology mapper does not pay much attention to relations among patterns. Each pattern is tried to match independently. A novel pattern matching algorithm that does not require patterns to be decomposed and couple speeding up techniques utilizing inter-relations among cells are described. These methods are very effective for large cell libraries with complex cells. Experimental results show that our methods gain matching time up to 40 times faster.