Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications

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Bibliographic Details
Published inACM transactions on architecture and code optimization
Format Journal Article
LanguageEnglish
Published 01.03.2023
Online AccessGet full text
ISSN1544-3566
1544-3973
DOI10.1145/3575861

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ISSN:1544-3566
1544-3973
DOI:10.1145/3575861