G-MAC An Application-Specific MAC/Co-Processor Synthesizer

• Published in: Design, Automation, and Test in Europe: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1; 03-07 Mar. 2003 p. 11134
• Main Authors: Chang, Alex C. -Y., Kuo, Wu-An, Wu, Allen C. -H., Hwang, TingTing
• Format: Conference Proceeding
• Language: English
• Published: Washington, DC, USA IEEE Computer Society 03.03.2003
• Series: ACM Conferences
• Subjects: Computer systems organization > Architectures > Parallel architectures > Interconnection architectures; Computer systems organization > Architectures > Parallel architectures > Very long instruction word; Computer systems organization > Architectures > Serial architectures > Complex instruction set computing; Computer systems organization > Architectures > Serial architectures > Reduced instruction set computing; Hardware > Electronic design automation > High-level and register-transfer level synthesis > Datapath optimization
• ISBN: 0769518702; 9780769518701
• ISSN: 1530-1591
• DOI: 10.5555/789083.1022888

A modern special-purpose processor (e.g., for image and graphical applications) usually contains a set of instructions supporting complex multiply-operations. These instructions perform a variety of multiply-operations with various data bitwidths and concurrent-execution requirements. For instance, such an instruction set may include instructions to perform signed/unsigned 32X32, signed/unsigned dual 16X16, signed/unsigned 8X8 MAC, and etc. Typically, co-processor or a complex MAC (Multiplier-ACcumulator) unit is required to execute those instructions. Developing such a complex MAC/co-processor involves a series of design tasks including micro-architecture design, component allocation/binding, interconnect binding, pipeline insertion and control generation. This design process is non-trivial, time-consuming and error-prone, which is usually performed by experienced design engineers. In this paper, we present synthesis method for application-specific MAC/co-processor generation. The MAC/co-processor synthesis problem is defined as: Given a set of instructions and the number of execution cycles for each instruction, generate a MAC/co-processor design (including a data-path and control unit) such that the total area-cost is minimized subject to the given execution-cycle constraints. The MAC/co-processor generation consists of the following two steps. In the first step, we determine a set of minimum-cost components required to realize the given instruction set. In the second step, we perform micro-architectural-level synthesis tasks, including component mapping, interconnect synthesis, pipeline insertion, and control synthesis to generate the MAC/co-processor design.