Simultaneous transistor pairing and placement for CMOS standard cells

This paper presents an integer linear programming approach to transistor placement problem for CMOS standard cells with objectives of minimizing cell width, wiring density, wiring length, diffusion contour roughness, and misalignments of common ploy gates. Our approach considers transistor pairing a...

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Bibliographic Details
Published in2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) pp. 1647 - 1652
Main Authors Ang Lu, Hsueh-Ju Lu, En-Jang Jang, Yu-Po Lin, Chun-Hsiang Hung, Chun-Chih Chuang, Rung-Bin Lin
Format Conference Proceeding
LanguageEnglish
Published EDAA 01.03.2015
Subjects
Layout
Logic gates
Runtime
standard cell
transistor folding
transistor pairing
Transistor placement
Transistors
Wires
Wiring
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ISSN1530-1591
DOI10.5555/2755753.2757194

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Summary:This paper presents an integer linear programming approach to transistor placement problem for CMOS standard cells with objectives of minimizing cell width, wiring density, wiring length, diffusion contour roughness, and misalignments of common ploy gates. Our approach considers transistor pairing and transistor placement simultaneously. It can achieve a smaller number of transistor chains than the well-known bipartite approach. About 31% of the 185 cells created by it have smaller widths and no cells whose widths are larger than their handcrafted counterparts.
ISSN:1530-1591
DOI:10.5555/2755753.2757194