Process variation tolerant SRAM array for ultra low voltage applications

• Published in: 2008 45th ACM/IEEE Design Automation Conference pp. 108 - 113
• Main Authors: Kulkarni, Jaydeep P., Kim, Keejong, Park, Sang Phill, Roy, Kaushik
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 08.06.2008; IEEE
• Series: ACM Conferences
• Subjects: Application software; Dynamic voltage scaling; Feedback; Hardware > Integrated circuits > Semiconductor memory; Low voltage; Low voltage/sub-threshold SRAM; Power dissipation; Process Tolerance; Random access memory; Robustness; Schmitt Trigger SRAM; Testing; Threshold voltage; Trigger circuits; Schmitt trigger SRAM; process tolerance; low voltage/sub-threshold SRAM
• ISBN: 1605581151; 9781605581156
• ISSN: 0738-100X
• DOI: 10.1145/1391469.1391498

In this work, we propose a Schmitt Trigger (ST) based differential sensing SRAM bitcell that can operate at ultra-low supply voltage. The proposed Schmitt Trigger SRAM cell addresses the fundamental conflicting design requirement of read versus write operation of a conventional 6T cell. Schmitt Trigger operation gives better read-stability and as well as better writeability compared to the standard 6T cell. The proposed ST bitcell incorporates a built-in feedback mechanism, achieving process variation tolerance - a must for future nano-scaled technology nodes. Measurements on 10 test-chips fabricated in 130nm technology show that the proposed Schmitt Trigger bitcell gives 58% higher read Static Noise Margin (SNM), 2X higher writetrip-point and 120mV lower read Vmin compared to the conventional 6T cell. The ST SRAM array is operational at 150mV of supply voltage.