FastRoute 4.0 global router with efficient via minimization

• Published in: Proceedings of the 2009 Asia and South Pacific Design Automation Conference pp. 576 - 581
• Main Authors: Xu, Yue, Zhang, Yanheng, Chu, Chris
• Format: Conference Proceeding
• Language: English
• Published: Piscataway, NJ, USA IEEE Press 19.01.2009
• Series: ACM Conferences
• ISBN: 9781424427482; 1424427487
• DOI: 10.5555/1509633.1509768

The number of vias generated during the global routing stage is a critical factor for the yield of final circuits. However, most global routers only approach the problem by charging a cost for vias in the maze routing cost function. In this paper, we present a global router that addresses the via number optimization problem throughout the entire global routing flow. We introduce the via aware Steiner tree generation, 3-bend routing and layer assignment with careful ordering to reduce via count. We integrate these three techniques into FastRoute 3.0 and achieve significant reduction in both via count and runtime.