Architecting a secure wireless network-on-chip
With increasing integration in SoCs, the Network-on-Chip (NoC) connecting cores and accelerators is of paramount importance to provide low-latency and high-throughput communication. Due to limits to scaling of electrical wires in terms of energy and delay, especially for long multi-mm distances on-c...
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          | Published in | Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip pp. 1 - 8 | 
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| Main Authors | , , , | 
| Format | Conference Proceeding | 
| Language | English | 
| Published | 
        Piscataway, NJ, USA
          IEEE Press
    
        04.10.2018
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| Series | ACM Conferences | 
| Online Access | Get full text | 
| ISBN | 1538648938 9781538648933  | 
| DOI | 10.5555/3306619.3306635 | 
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| Summary: | With increasing integration in SoCs, the Network-on-Chip (NoC) connecting cores and accelerators is of paramount importance to provide low-latency and high-throughput communication. Due to limits to scaling of electrical wires in terms of energy and delay, especially for long multi-mm distances on-chip, alternate technologies such as Wireless Network-on-Chip (WNoC) have shown promise. WNoCs can provide low-latency one-hop broadcasts across the entire chip and can augment point-to-point multi-hop signaling over traditional wired NoCs. Thus, there has been a recent surge in research demonstrating the performance and energy benefits of WNoCs. However, little to no work has studied the additional security and fault tolerance challenges that are unique to WNoCs. In this work, we study potential threats related to denial-of-service, spoofing, and eaves-dropping attacks in WNoCs, due to malicious hardware trojans or faulty wireless components. We introduce Prometheus, a drop-in solution inside the network interface that provides protection from all three attacks, while adhering to the strict area, power and latency constraints of on-chip systems. | 
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| ISBN: | 1538648938 9781538648933  | 
| DOI: | 10.5555/3306619.3306635 |