TFET-based cellular neural network architectures

• Published in: Proceedings of the 2013 International Symposium on Low Power Electronics and Design pp. 236 - 241
• Main Authors: Palit, Indranil, Hu, X. Sharon, Nahas, Joseph, Niemier, Michael
• Format: Conference Proceeding
• Language: English
• Published: Piscataway, NJ, USA IEEE Press 04.09.2013
• Series: ACM Conferences
• Subjects: Applied computing > Physical sciences and engineering > Electronics; Computer systems organization > Architectures > Other architectures > Neural networks; Hardware > Hardware validation; low power; CNN; TFET; cellular neural networks; tunneling field effect transistor
• ISBN: 1479912352; 9781479912353
• DOI: 10.5555/2648668.2648728

It is well known that CMOS scaling trends are now accompanied by less desirable byproducts such as increased energy dissipation. To combat the aforementioned challenges, solutions are sought at both the device and architectural levels. With this context, this work focuses on embedding a low voltage device, a Tunneling Field Effect Transistor (TFET) within a Cellular Neural Network (CNN) -- a low power analog computing architecture. Our study shows that TFET-based CNN systems, aside from being fully functional, also provide significant power savings when compared to the conventional resistor-based CNN. Our initial studies suggest that power savings are possible by carefully engineering lower voltage, lower current TFET devices without sacrificing performance. Moreover, TFET-based CNN reduces implementation footprints by eliminating the hardware required to realize output transfer functions. Application dynamics are verified through simulations. We conclude the paper with a discussion of desired device characteristics for CNN architectures with enhanced functionality.