Graphene nano-ribbon field-effect transistors as future low-power devices

• Published in: Proceedings of the 2013 International Symposium on Low Power Electronics and Design pp. 151 - 156
• Main Authors: Chen, Ying-Yu, Sangai, Amit, Gholipour, Morteza, Chen, Deming
• Format: Conference Proceeding
• Language: English
• Published: Piscataway, NJ, USA IEEE Press 04.09.2013
• Series: ACM Conferences
• Subjects: Applied computing > Physical sciences and engineering > Electronics; Hardware > Electronic design automation > Physical design (EDA); Hardware > Hardware validation
• ISBN: 1479912352; 9781479912353
• DOI: 10.5555/2648668.2648708

The graphene nano-ribbon field effect transistor (GNRFET) is an emerging technology that received much attention in recent years. Recent work on GNRFET circuit simulations has shown that GNRFETs may have potential in low power applications. In this paper, we review the existing work on GNRFET circuit modeling, compare the two varieties of GNRFETs, Metal-Oxide-Semiconducting-(MOS-)type and Schottky-Barrier-(SB-)type GNRFETs, and thoroughly discuss and explore their respective strengths in terms of delay, power, and noise margin. From this point of view, we discuss their possible applications, especially the use towards low-power computing. Our simulations show that ideal (non-ideal) MOS-GNRFET consumes 18% (35%) and 54% (102%) total power as compared to high-performance (HP) Si-CMOS and low-power (LP) Si-CMOS, respectively. SB-GNRFET does not compare favorably to MOS-GNRFET in terms of power consumption. However, ideal (non-ideal) SB-GNRFET has 3% (5.4X) and 0.45% (83.5%) energy-delay product (EDP) compared to Si-CMOS (HP) and Si-CMOS (LP), respectively, while ideal (non-ideal) MOS-GNRFET has 8% (93%) and 1.25% (14.3%) EDP compared to Si-CMOS (HP) and Si-CMOS (LP), respectively.