Adaptive techniques for overcoming performance degradation due to aging in digital circuits

• Published in: Proceedings of the 2009 Asia and South Pacific Design Automation Conference pp. 284 - 289
• Main Authors: Kumar, Sanjay V., Kim, Chris H., Sapatnekar, Sachin S.
• Format: Conference Proceeding
• Language: English
• Published: Piscataway, NJ, USA IEEE Press 19.01.2009
• Series: ACM Conferences
• ISBN: 9781424427482; 1424427487
• DOI: 10.5555/1509633.1509709

Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent usage of Hf-based high-k dielectrics for gate leakage reduction, Positive Bias Temperature Instability (PBTI), the dual effect in NMOS transistors has also reached significant levels. Consequently, designers are required to build in substantial guard-bands into their designs, leading to large area and power overheads, in order to guarantee reliable operation over the lifetime of a chip. We propose a guard-banding technique based on adaptive body bias (ABB) and adaptive supply voltage (ASV), to recover the performance of an aged circuit, and compare its merits over previous approaches.