Write intensity prediction for energy-efficient non-volatile caches

• Published in: Proceedings of the 2013 International Symposium on Low Power Electronics and Design pp. 223 - 228
• Main Authors: Ahn, Junwhan, Yoo, Sungjoo, Choi, Kiyoung
• Format: Conference Proceeding
• Language: English
• Published: Piscataway, NJ, USA IEEE Press 04.09.2013
• Series: ACM Conferences
• Subjects: Applied computing > Physical sciences and engineering > Electronics; Hardware > Hardware validation; Hardware > Integrated circuits > Semiconductor memory > Dynamic memory
• ISBN: 1479912352; 9781479912353
• DOI: 10.5555/2648668.2648724

This paper presents a novel concept called write intensity prediction for energy-efficient non-volatile caches as well as the architecture that implements the concept. The key idea is to correlate write intensity of cache blocks with addresses of memory access instructions that incur cache misses of those blocks. The predictor keeps track of instructions that tend to load write-intensive blocks and utilizes that information to predict write intensity of blocks. Based on this concept, we propose a block placement strategy driven by write intensity prediction for SRAM/STT-RAM hybrid caches. Experimental results show that the proposed approach reduces write energy consumption by 55% on average compared to the existing hybrid cache architecture.