A multilevel analytical placement for 3D ICs

• Published in: Proceedings of the 2009 Asia and South Pacific Design Automation Conference pp. 361 - 366
• Main Authors: Cong, Jason, Luo, Guojie
• Format: Conference Proceeding
• Language: English
• Published: Piscataway, NJ, USA IEEE Press 19.01.2009
• Series: ACM Conferences
• Subjects: Information systems; Information systems > Data management systems; Information systems > Data management systems > Database administration; Information systems > Data management systems > Database administration > Data dictionaries; Theory of computation; Theory of computation > Design and analysis of algorithms; Theory of computation > Design and analysis of algorithms > Mathematical optimization
• ISBN: 9781424427482; 1424427487
• DOI: 10.5555/1509633.1509725

In this paper we propose a multilevel non-linear programming based 3D placement approach that minimizes a weighted sum of total wirelength and TS via number subject to area density constraints. This approach relaxes the discrete layer assignments so that they are continuous in the z-direction and the problem can be solved by an analytical global placer. A key idea is to do the overlap removal and device layer assignment simultaneously by adding a density penalty function for both area & TS via density constraints. Experimental results show that this analytical placer in a multilevel framework is effective to achieve trade-offs between wirelength and TS via number. Compared to the recently published transformation-based 3D placement method [1], we are able to achieve on average 12% shorter wirelength and 29% fewer TS via compared to their cases with best wirelength; we are also able to achieve on average 20% shorter wirelength and 50% fewer TS via number compared to their cases with best TS via numbers.