Stable and efficient reduction of substrate model networks using congruence transforms

• Published in: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design pp. 207 - 214
• Main Authors: Kerns, Kevin J., Wemple, Ivan L., Yang, Andrew T.
• Format: Conference Proceeding
• Language: English
• Published: Washington, DC, USA IEEE Computer Society 01.12.1995
• Series: ACM Conferences
• Subjects: Applied computing > Physical sciences and engineering; Hardware > Electronic design automation > Physical design (EDA); mixed-signal integrated circuits; rc network reduction; pade approximation; substrate noise; lanczos process; congruence transform; stability; voronoi tesselation
• ISBN: 9780818672132; 0818672137
• DOI: 10.5555/224841.224882

Parasitic analog-digital noise coupling has been identified as a key issue facing designers of mixed-signal integrated circuits. In particular, signal cross talk through the common chip substrate has become increasingly problematic. This paper demonstrates a new methodology for developing simulation, synthesis, and verification models to analyze the global electrical behavior of the non-ideal semiconductor substrate. RC substrate network models, which are generated via a triangular discretization method, are accurately approximated for subsequent analysis by an efficient reduction algorithm. This algorithm utilizes the well-conditioned Lanczos process to formulate Pade approximations of the network port admittance. Congruence transformations are employed to ensure stability, and to create reduced networks which are easily realizable with SPICE-compatible RC elements. For validation, the strategy has been successfully applied to several mixed-signal circuit examples.