High-performance, low-power resonant clocking

Clock distribution networks consume a significant portion of on-chip power. Traditional buffered clock distribution power is limited by frequency, capacitance, and activity rates. Resonant clock distributions can reduce this power by "recycling" energy on-chip and reducing the overall cloc...

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Published inProceedings of the International Conference on Computer-Aided Design pp. 742 - 745
Main Authors Guthaus, Matthew R., Taskin, Baris
Format Conference Proceeding
LanguageEnglish
Japanese
Published New York, NY, USA ACM 05.11.2012
SeriesACM Conferences
Subjects
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ISBN9781450315739
1450315739
DOI10.1145/2429384.2429545

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Abstract Clock distribution networks consume a significant portion of on-chip power. Traditional buffered clock distribution power is limited by frequency, capacitance, and activity rates. Resonant clock distributions can reduce this power by "recycling" energy on-chip and reducing the overall clock power. This tutorial introduces recent techniques for distributed-LC, traveling wave, and standing wave resonant clock distributions. In particular, the tutorial discusses the recent developments and open research problems. The tutorial covers both circuits, computer-aided design algorithms and methodologies for resonant clocking.
AbstractList Clock distribution networks consume a significant portion of on-chip power. Traditional buffered clock distribution power is limited by frequency, capacitance, and activity rates. Resonant clock distributions can reduce this power by "recycling" energy on-chip and reducing the overall clock power. This tutorial introduces recent techniques for distributed-LC, traveling wave, and standing wave resonant clock distributions. In particular, the tutorial discusses the recent developments and open research problems. The tutorial covers both circuits, computer-aided design algorithms and methodologies for resonant clocking.
Author Guthaus, Matthew R.
Taskin, Baris
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  email: taskin@coe.drexel.edu
  organization: Drexel University, Philadelphia, PA
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Snippet Clock distribution networks consume a significant portion of on-chip power. Traditional buffered clock distribution power is limited by frequency, capacitance,...
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SubjectTerms Applied computing -- Arts and humanities -- Architecture (buildings) -- Computer-aided design
Applied computing -- Physical sciences and engineering -- Engineering -- Computer-aided design
Hardware -- Emerging technologies
Hardware -- Hardware validation
Hardware -- Very large scale integration design
Title High-performance, low-power resonant clocking
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