VLSI test principles and architectures : design for testability

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of indu...

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Bibliographic Details
Other Authors: Wang, Laung-Terng, (Editor), Wu, Cheng-Wen, EE Ph. D., (Editor), Wen, Xiaoqing, (Editor)
Format: eBook
Language: English
Published: Amsterdam ; Boston : Elsevier Morgan Kaufmann Publishers, [2006]
Series: Morgan Kaufmann series in systems on silicon.
Subjects:
Integrated circuits > Very large scale integration > Testing.
Integrated circuits > Very large scale integration > Design.
Integrated circuits > Very large scale integration > Design and construction.
elektronické knihy
electronic books
ISBN: 9780080474793
0080474799
9780123705976
0123705975
Physical Description: 1 online resource (xxx, 777 pages) : illustrations

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LEADER 04590cam a2200457 i 4500
001 kn-ocn162573568
003 OCoLC
005 20240717213016.0
006 m o d
007 cr cn|||||||||
008 070806t20062006ne a ob 001 0 eng d
040 |a OPELS  |b eng  |e rda  |e pn  |c OPELS  |d OCLCG  |d OCLCQ  |d N$T  |d EBLCP  |d MERUC  |d E7B  |d IDEBK  |d UMI  |d CEF  |d NHM  |d DEBSZ  |d KNOVL  |d OCLCO  |d OCLCQ  |d KNOVL  |d WAU  |d KNOVL  |d OCLCF  |d OCLCQ  |d CUS  |d OCLCQ  |d OCLCO  |d OCLCQ  |d KNOVL  |d YDXCP  |d OCLCO  |d OCLCQ  |d OCLCO  |d OCLCQ  |d OCLCO  |d COO  |d OCLCO  |d OCLCQ  |d OCLCO  |d AZK  |d OCLCO  |d AGLDB  |d LVT  |d TOA  |d OCLCO  |d MOR  |d PIFAG  |d ZCU  |d OCLCQ  |d JBG  |d U3W  |d BUF  |d REB  |d STF  |d WRM  |d D6H  |d OCLCO  |d OCLCQ  |d VTS  |d ICG  |d INT  |d VT2  |d AU@  |d OCLCO  |d OCLCQ  |d OCLCA  |d REC  |d OCLCO  |d OCLCQ  |d MERER  |d LEAUB  |d OCLCO  |d OCLCQ  |d DKC  |d OCLCQ  |d OCLCO  |d OCLCQ  |d K6U  |d LUN  |d OCLCQ  |d OCLCO  |d M8D  |d OCLCO  |d OCLCQ  |d KSU  |d OCL  |d GZM  |d OCLCQ  |d OCLCO  |d OCLCL  |d EZC  |d UKCRE 
020 |a 9780080474793  |q (electronic bk.) 
020 |a 0080474799  |q (electronic bk.) 
020 |z 9780123705976  |q (hbk.) 
020 |z 0123705975  |q (hbk.) 
035 |a (OCoLC)162573568  |z (OCoLC)123441360  |z (OCoLC)154703466  |z (OCoLC)299750751  |z (OCoLC)434023516  |z (OCoLC)441775657  |z (OCoLC)648178245  |z (OCoLC)772045718  |z (OCoLC)856952279  |z (OCoLC)961513666  |z (OCoLC)962682390  |z (OCoLC)972045931  |z (OCoLC)988532552  |z (OCoLC)992014050  |z (OCoLC)1026460121  |z (OCoLC)1034946424  |z (OCoLC)1035711655  |z (OCoLC)1037790220  |z (OCoLC)1038699337  |z (OCoLC)1044324180  |z (OCoLC)1055404986  |z (OCoLC)1056398101  |z (OCoLC)1058118432  |z (OCoLC)1060909266  |z (OCoLC)1153046457 
245 0 0 |a VLSI test principles and architectures :  |b design for testability /  |c edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen. 
264 1 |a Amsterdam ;  |a Boston :  |b Elsevier Morgan Kaufmann Publishers,  |c [2006] 
264 4 |c ©2006 
300 |a 1 online resource (xxx, 777 pages) :  |b illustrations 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
490 1 |a The Morgan Kaufmann series in systems on silicon 
504 |a Includes bibliographical references and index. 
505 0 |a Design for testability / Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez -- Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker -- Test generation / Michael S. Hsiao -- Logic built-in self-test / Laung-Terng (L.-T.) Wang -- Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba -- Logic diagnosis / Shi-Yu Huang -- Memory testing and built-in self-test / Cheng-Wen Wu -- Memory diagnosis and built-in self-repair / Cheng-Wen Wu -- Boundary scan and core-based testing / Kuen-Jong Lee -- Analog and mixed-signal testing / Chauchin Su -- Test technology trends in the nanometer age / Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang. 
506 |a Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty 
520 |a This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website. 
590 |a Knovel  |b Knovel (All titles) 
650 0 |a Integrated circuits  |x Very large scale integration  |x Testing. 
650 0 |a Integrated circuits  |x Very large scale integration  |x Design. 
650 0 |a Integrated circuits  |x Very large scale integration  |x Design and construction. 
655 7 |a elektronické knihy  |7 fd186907  |2 czenas 
655 9 |a electronic books  |2 eczenas 
700 1 |a Wang, Laung-Terng,  |e editor. 
700 1 |a Wu, Cheng-Wen,  |c EE Ph. D.,  |e editor.  |1 https://id.oclc.org/worldcat/entity/E39PCjxmfVgHb6DmrxWJWjR4tq 
700 1 |a Wen, Xiaoqing,  |e editor. 
776 0 8 |i Print version:  |t VLSI test principles and architectures.  |d Amsterdam ; Boston : Elsevier Morgan Kaufmann Publishers, ©2006  |z 0123705975  |z 9780123705976  |w (DLC) 2006006869  |w (OCoLC)64624834 
830 0 |a Morgan Kaufmann series in systems on silicon. 
856 4 0 |u https://proxy.k.utb.cz/login?url=https://app.knovel.com/hotlink/toc/id:kpVLSITPA2/vlsi-test-principles?kpromoter=marc  |y Full text 

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