Testing of interposer-based 2.5D integrated circuits

• Main Authors: Wang, Ran (Author), Chakrabarty, Krishnendu (Author)
• Format: Electronic eBook
• Language: English
• Published: Cham, Switzerland : Springer, 2017.
• Subjects: Integrated circuits.; elektronické knihy; electronic books
• ISBN: 9783319547145; 9783319547138
• Physical Description: 1 online resource (xiv, 182 pages) : illustrations (some color)

This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer,...

Table of Contents:

• Preface; Acknowledgements; Contents; 1 Introduction; 1.1 The Evolution of 2.5D ICs; 1.1.1 3D ICs: A Paradigm Shift from Traditional Integrated Circuits; 1.1.2 2.5D ICs: An Alternative to 3D ICs; 1.2 Research Challenges and Motivation; 1.2.1 Pre-bond Interposer Testing; 1.2.2 Lack of Test Access; 1.2.3 Limited Ability for At-Speed Testing; 1.2.4 High-Density I/O Ports and Interconnects; 1.2.5 Reduced Number of Test Pins; 1.2.6 High Power Consumption; 1.3 Emerging Solutions for the Testing of 2.5D ICs; 1.4 Outline of the Book; References; 2 Pre-bond Testing of the Silicon Interposer.
• 2.1 Background2.2 Proposed Test Architecture and Procedures; 2.2.1 Definition of Die Footprint; 2.2.2 Test Architecture; 2.2.3 Assembly and Test Flow; 2.2.4 Test Procedures; 2.2.5 Weighted Critical Area; 2.3 Test-Path Design; 2.3.1 Optimization Problem; 2.3.2 Proposed Algorithm; 2.4 Experimental Results; 2.4.1 Testing the Horizontal Interconnects; 2.4.2 Testing for Vertical Interconnects; 2.4.3 Evaluation of the Test-Path Design Method; 2.5 Conclusion; References; 3 Post-bond Scan-Based Testing of Interposer Interconnects; 3.1 Problem Statement; 3.2 Proposed Test Architecture.
• 3.3 Test Application3.3.1 Open/Short-Defect Testing; 3.3.2 Delay-Defect Testing; 3.3.3 Test Structures for Bi-directional I/Os; 3.4 Integration with IEEE 1149.1; 3.5 Simulation Results; 3.5.1 Detection Capability for Open Defects; 3.5.2 Detection Capability for Short Defects; 3.5.3 Detection Capability for Delay Defects; 3.5.4 Architecture Simulation; 3.5.5 Area Overhead; 3.6 Conclusion; References; 4 Test Architecture and Test-Path Scheduling; 4.1 Proposed Test Architecture; 4.1.1 Boundary-Scan Structure; 4.1.2 Modified TAP Controller; 4.1.3 Boundary-Scan Cells and Circuit Block.
• 4.1.4 Test Procedures4.2 Test-Path Design and Scheduling; 4.2.1 Structure of Additional Test Paths; 4.2.2 Minimization of Total Interconnect Test Cost; 4.2.3 Optimization in Alternative Scenarios; 4.2.4 Placement of Dies on the Test Path; 4.3 Simulation Results; 4.3.1 Test Architecture Simulation Results; 4.3.2 Case Study; 4.3.3 Area Overhead; 4.3.4 Test-Path Design and Scheduling Results; 4.4 Conclusion; References; 5 Built-In Self-Test; 5.1 Related Prior Work; 5.2 Proposed BIST Architecture; 5.3 BIST Components; 5.3.1 Self-configuration of the In-BSC; 5.3.2 Pattern Generator.
• 5.3.3 Response Compactor5.3.4 BIST Controller; 5.4 Test Scheduling and Optimization; 5.5 Simulation Results; 5.5.1 BIST Architecture Simulation; 5.5.2 Case Study; 5.5.3 Overhead Analysis; 5.5.4 Test Scheduling Results; 5.6 Conclusion; References; 6 ExTest Scheduling and Optimization; 6.1 Problem Statement; 6.2 Test Architecture and Current Solution; 6.3 Proposed Scheduling Strategies; 6.3.1 Scheduling Strategy for SoC Dies with Dedicated Wrappers; 6.3.2 Scheduling Strategy for Extremely Large SoC Dies; 6.4 Schedule Optimization; 6.4.1 Sharing of Inputs; 6.4.2 Output Removal.