Electromigration inside logic cells : modeling, analyzing and mitigating signal electromigration in NanoCMOS

This book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power. The authors are the first to analyze and propose a solution for t...

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Bibliographic Details
Main Authors: Posser, Gracieli, (Author), Sapatnekar, Sachin S., 1967- (Author), Reis, Ricardo, (Author)
Format: eBook
Language: English
Published: Cham, Switzerland : Springer, 2017.
Subjects:
Logic circuits.
Electrodiffusion.
elektronické knihy
electronic books
ISBN: 9783319488998
9783319488981
Physical Description: 1 online resource

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Table of contents

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100 1 |a Posser, Gracieli,  |e author. 
245 1 0 |a Electromigration inside logic cells :  |b modeling, analyzing and mitigating signal electromigration in NanoCMOS /  |c Gracieli Posser, Sachin S. Sapatnekar, Ricardo Reis. 
264 1 |a Cham, Switzerland :  |b Springer,  |c 2017. 
300 |a 1 online resource 
336 |a text  |b txt  |2 rdacontent 
337 |a počítač  |b c  |2 rdamedia 
338 |a online zdroj  |b cr  |2 rdacarrier 
505 0 |a Preface; Acknowledgments; Contents; List of Figures; List of Tables; Abbreviations; 1 Introduction; 1.1 Reliability and Electromigration; 1.2 Electromigration in Future Technologies; 1.3 Motivation and Contributions; 1.4 Monograph Outline; 2 State of the Art; 2.1 Mitigating the EM Effects in Different IC Design Flow Stages; 2.1.1 Managing Electromigration in Logic Designs; 2.1.2 Electromigration Impact in Future Technologies; 2.1.3 Smart Non-default Routing for Clock Power Reduction; 2.1.4 Impacts of Electromigration Awareness. 
505 8 |a 2.2 Mitigating the EM Effects in Different Types of Interconnections2.2.1 TSVs; 2.2.2 Power Delivery Network; 2.2.3 Clock Network; 2.2.4 Vias; 2.2.5 Signal Interconnects; 2.2.6 Cell-Internal EM; 2.2.6.1 Accurate Current Estimation for Interconnect Reliability Analysis (Jain12); 2.2.6.2 CMOS Inverter and Standard Cell the Same(patenteempindomae2001cmos); 2.3 Summary of Related Works; 2.4 Conclusions; 3 Modeling Cell-Internal EM; 3.1 Modeling Time-to-Failure Under EM; 3.2 Joule Heating; 3.2.1 Local Hot Spots from Joule Heating; 3.3 Current Divergence. 
505 8 |a 3.3.1 New Electromigration Validation: Via Node Vector Method3.3.2 Applying Current Divergence in the Proposed EM Model; 3.3.3 The Impact of Blech Length on Cell-Internal Interconnects; 3.4 Conclusions; 4 Current Calculation; 4.1 Current Flows Using Graph Traversals; 4.2 Algebra for Average/RMS Current Updates; 4.2.1 Algebra for Computing Average Current; 4.2.2 Algebra for Computing the RMS Current; 4.2.2.1 Example; 4.3 Results; 5 Experimental Setup; 6 Results; 6.1 The Electromigration Effects for Different Logic Gates; 6.1.1 NAND2_X2 and NOR2_X2 Gates. 
505 8 |a 6.1.1.1 TTF Improvement by Layout Modifications6.1.2 AOI21_X2; 6.1.2.1 TTF Improvement by Layout Modifications; 6.1.3 NOR2_X4; 6.1.4 INV_X16; 6.2 Conclusion; 7 Analyzing the Electromigration Effects on Different Metal Layers and Different Wire Lengths; 7.1 Experimental Setup; 7.2 Simulation Results; 7.3 Conclusion; 8 Conclusions; 8.1 Future Works; A Impact on Physical Synthesis Considering Different Amounts of Instances with EM Awareness; B Coupling Capacitance Currents; References. 
504 |a Includes bibliographical references. 
506 |a Plný text je dostupný pouze z IP adres počítačů Univerzity Tomáše Bati ve Zlíně nebo vzdáleným přístupem pro zaměstnance a studenty 
520 |a This book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power. The authors are the first to analyze and propose a solution for the electromigration effects inside logic cells of a circuit. They show in this book that an interconnect inside a cell can fail reducing considerably the circuit lifetime and they demonstrate a methodology to optimize the lifetime of circuits, by placing the output, Vdd and Vss pin of the cells in the less critical regions, where the electromigration effects are reduced. Readers will be enabled to apply this methodology only for the critical cells in the circuit, avoiding impact in the circuit delay, area and performance, thus increasing the lifetime of the circuit without loss in other characteristics. 
590 |a SpringerLink  |b Springer Complete eBooks 
650 0 |a Logic circuits. 
650 0 |a Electrodiffusion. 
655 7 |a elektronické knihy  |7 fd186907  |2 czenas 
655 9 |a electronic books  |2 eczenas 
700 1 |a Sapatnekar, Sachin S.,  |d 1967-  |e author. 
700 1 |a Reis, Ricardo,  |e author. 
776 0 8 |i Printed edition:  |z 9783319488981 
856 4 0 |u https://proxy.k.utb.cz/login?url=https://link.springer.com/10.1007/978-3-319-48899-8  |y Plný text 
992 |c NTK-SpringerENG 
999 |c 99606  |d 99606 

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