System and method for chip testing
A system and method for chip testing is disclosed. The present invention's method includes the steps of establishing a communications link between a chip and a computer tester; receiving on the chip an initial test algorithm over a communications link; testing the chip, using a built-in self-te...
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| Main Author | |
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| Format | Patent |
| Language | English |
| Published |
26.12.2002
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| Online Access | Get full text |
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| Abstract | A system and method for chip testing is disclosed. The present invention's method includes the steps of establishing a communications link between a chip and a computer tester; receiving on the chip an initial test algorithm over a communications link; testing the chip, using a built-in self-test (BIST) circuit on the chip, in accordance with the initial algorithm; collecting a set of failure information in response to testing; and transmitting the failure information from the chip to the computer over the communications link. The present invention's system includes: a communications link; a computer, operating a set of chip testing software; and a chip under test coupled to the computer by the communications link, having, a memory array; and a BIST module for testing the memory array in response to test algorithms received from the computer and transmitting those addresses within the memory array which failed testing. |
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| AbstractList | A system and method for chip testing is disclosed. The present invention's method includes the steps of establishing a communications link between a chip and a computer tester; receiving on the chip an initial test algorithm over a communications link; testing the chip, using a built-in self-test (BIST) circuit on the chip, in accordance with the initial algorithm; collecting a set of failure information in response to testing; and transmitting the failure information from the chip to the computer over the communications link. The present invention's system includes: a communications link; a computer, operating a set of chip testing software; and a chip under test coupled to the computer by the communications link, having, a memory array; and a BIST module for testing the memory array in response to test algorithms received from the computer and transmitting those addresses within the memory array which failed testing. |
| Author | Ku, Joseph |
| Author_xml | – sequence: 1 givenname: Joseph surname: Ku fullname: Ku, Joseph |
| BookMark | eNrjYmDJy89L5WRQCq4sLknNVUjMS1HITS3JyE9RSMsvUkjOyCxQKEktLsnMS-dhYE1LzClO5YXS3Ayabq4hzh66pcUFiSWpeSXF8YkFBTmZyYklmfl5xfFGBgZGBoaWlobGZsakqAUAj4kumw |
| ContentType | Patent |
| DBID | EFI |
| DatabaseName | USPTO Published Applications |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: EFI name: USPTO Published Applications url: http://www.uspto.gov/patft/index.html sourceTypes: Open Access Repository |
| DeliveryMethod | fulltext_linktorsrc |
| ExternalDocumentID | 20020199136 |
| GroupedDBID | EFI |
| ID | FETCH-uspatents_applications_200201991363 |
| IEDL.DBID | EFI |
| IngestDate | Sun Mar 05 22:31:10 EST 2023 |
| IsOpenAccess | true |
| IsPeerReviewed | false |
| IsScholarly | false |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-uspatents_applications_200201991363 |
| OpenAccessLink | https://patentcenter.uspto.gov/applications/09892291 |
| ParticipantIDs | uspatents_applications_20020199136 |
| PublicationCentury | 2000 |
| PublicationDate | 20021226 |
| PublicationDateYYYYMMDD | 2002-12-26 |
| PublicationDate_xml | – month: 12 year: 2002 text: 20021226 day: 26 |
| PublicationDecade | 2000 |
| PublicationYear | 2002 |
| Score | 2.5320191 |
| Snippet | A system and method for chip testing is disclosed. The present invention's method includes the steps of establishing a communications link between a chip and a... |
| SourceID | uspatents |
| SourceType | Open Access Repository |
| Title | System and method for chip testing |
| URI | https://patentcenter.uspto.gov/applications/09892291 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQMU1LAm3ITNFNBLaGdU0SDY11LYAVvW6ycZKlaWJiciJkH7evn5lHqIlXhGkEdFMYaC9MAbCFlVcCWpiYWqRXWlxQkg9eXYkym2tgaWFpZATass5sYQbu8rh5cjNwAlWDNRcjVRBuggxsAWBRIQam1DwRBiXIQeAKwG66AuSOZgVg41AhOSOzQKEEdK5FXroog6aba4izhy7cwHhk60EXNwJrTWC7ytjMWIyBBdhLT5VgUEhKNrBITbIwMk9JMTaxTLG0SAEGg4mRiXkyMMckJZlIMigRNk-KGEXSDFywK0mMzGQYWEqKSlNlgTVjSZIcOCgACvFtVg |
| linkProvider | USPTO |
| linkToPdf | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1LSwMxEB60io-TolLfoXjxEK2b7OusXVofZQ8KvS15bK2g6dJN8e872ajsTa8hDMOEZGbI930DcBFOpSNkaiqwGqZc3DCaYKKnisk0FEIJz-N-GkfDF34_CSff9OiGC_OB14hW6Et9tawrO2_Alfi8-4OnXvzZaQQapz7wad7nQud6eu3ABn2H42HRKqxFLA4cwGuQjbZhEw1h4WZs3Uod2Q6s583qLqyUZg96XiKcYANP_PRmgmUjUbO3ilineGFe9-EyGzzfDumvwaL9zVy0fGAH0MH-vewCkaqflDIJYq0ZT3WaaAwQD3is8C5JyQ-h97e9o_9sOoeN_C4rHkfjh2PY-plbEkQn0LGLZXmK6dPKsyYqX2yDeJQ |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=System+and+method+for+chip+testing&rft.inventor=Ku%2C+Joseph&rft.date=2002-12-26&rft.externalDBID=n%2Fa&rft.externalDocID=20020199136 |