METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE USING A MODELING ALGORITHM TO MODEL THE PROXIMITY EFFECT FROM THE SUB-LAYER

A method for forming a circuit layout comprises performing process proximity effect modeling based on process proximity effects caused by a sub-layer, wherein the sub-layer comprises an active layer positioned under a gate poly, and wherein performing the process proximity effect modeling includes c...

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Format Patent
LanguageEnglish
Published 04.02.2011
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Summary:A method for forming a circuit layout comprises performing process proximity effect modeling based on process proximity effects caused by a sub-layer, wherein the sub-layer comprises an active layer positioned under a gate poly, and wherein performing the process proximity effect modeling includes calculating a pattern density of the sub-layer, incorporating results of the process proximity effect modeling into a modeling algorithm, and performing proximity correction using the results to manipulate a layout of a mask to be used when forming the circuit layout by photolithography.