METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE USING A MODELING ALGORITHM TO MODEL THE PROXIMITY EFFECT FROM THE SUB-LAYER
A method for forming a circuit layout comprises performing process proximity effect modeling based on process proximity effects caused by a sub-layer, wherein the sub-layer comprises an active layer positioned under a gate poly, and wherein performing the process proximity effect modeling includes c...
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| Format | Patent |
|---|---|
| Language | English |
| Published |
04.02.2011
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| Online Access | Get full text |
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| Abstract | A method for forming a circuit layout comprises performing process proximity effect modeling based on process proximity effects caused by a sub-layer, wherein the sub-layer comprises an active layer positioned under a gate poly, and wherein performing the process proximity effect modeling includes calculating a pattern density of the sub-layer, incorporating results of the process proximity effect modeling into a modeling algorithm, and performing proximity correction using the results to manipulate a layout of a mask to be used when forming the circuit layout by photolithography. |
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| AbstractList | A method for forming a circuit layout comprises performing process proximity effect modeling based on process proximity effects caused by a sub-layer, wherein the sub-layer comprises an active layer positioned under a gate poly, and wherein performing the process proximity effect modeling includes calculating a pattern density of the sub-layer, incorporating results of the process proximity effect modeling into a modeling algorithm, and performing proximity correction using the results to manipulate a layout of a mask to be used when forming the circuit layout by photolithography. |
| BookMark | eNqNys0KgkAUBWAXtejvHe6qnZAJtdbxjjPgNDFeI1ciYSDIKIwtevtCe4BW53C-s_YWtrfNynsrJKET4NoAj2IjWUTykkIEOSrJ9CUpGH0twZtkCEU-o9IJZlPNUm0kCQWk5xVIIFyNvkslqQTkHBkBN1pNkhexn0Ulmq23fNada3a_3Hh7jsSE_3JDPTZ2dFU9DF37qMe2t64KwsMxCE_n8O_jB_BdQYU |
| ContentType | Patent |
| DBID | EFI |
| DatabaseName | USPTO Published Applications |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: EFI name: USPTO Published Applications url: http://www.uspto.gov/patft/index.html sourceTypes: Open Access Repository |
| DeliveryMethod | fulltext_linktorsrc |
| ExternalDocumentID | 20120204135 |
| GroupedDBID | EFI |
| ID | FETCH-uspatents_applications_130213673 |
| IEDL.DBID | EFI |
| IngestDate | Sun Mar 05 22:11:18 EST 2023 |
| IsOpenAccess | true |
| IsPeerReviewed | false |
| IsScholarly | false |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-uspatents_applications_130213673 |
| OpenAccessLink | https://patentcenter.uspto.gov/applications/13021367 |
| ParticipantIDs | uspatents_applications_13021367 |
| PublicationCentury | 2000 |
| PublicationDate | 20110204 |
| PublicationDateYYYYMMDD | 2011-02-04 |
| PublicationDate_xml | – month: 02 year: 2011 text: 20110204 day: 04 |
| PublicationDecade | 2010 |
| PublicationYear | 2011 |
| Score | 2.6799834 |
| Snippet | A method for forming a circuit layout comprises performing process proximity effect modeling based on process proximity effects caused by a sub-layer, wherein... |
| SourceID | uspatents |
| SourceType | Open Access Repository |
| Title | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE USING A MODELING ALGORITHM TO MODEL THE PROXIMITY EFFECT FROM THE SUB-LAYER |
| URI | https://patentcenter.uspto.gov/applications/13021367 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwhV3dT8MgEL-4xUR90qjxWx6Mb5htdgQfu5auNW1ZOmq6pwVW9jiXrXvwvxeYmvm0N3IHhCOBux93xwE8aanmUpuDZGtGY28-o5hqNcOaqL6qJZU9V70hy0lceu9Vv_pJCrO5MEtjYS0aG5ioVy-b9bL5dNGV_7y51tdmfxprQYsSB3mi5ASOTG83eL2jIKJTOBw56hkc6MU5fGVMxDxEBmKhyB8ULl03HyIfja3cPA_LQBheyD6SgCFb-8IyMx6y1DXTIS8SEWdI8C0ViZihUcEre9lMkDEvWSBQVPDMccblAKf-hBUX8BwxEcT4b53TXammv1K9XkLbIH99BYgQXb95SteEdjyDZKQ06lp7uqtmhKq6ew2Peya72dvjFo63z6Q93PHuoN2sNvre6NlGPbiN_Qaj6ICc |
| linkProvider | USPTO |
| linkToPdf | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwhR1dT8IwsFE0fjxp1PhNH4xvNWyMOh9h6xjK6DKKgSfSsvKkg8iI8d977Yzhjbem11zurun1rr0PhB60VHOp4SCZntHEm8984ms1I5qqlsqlL13bvSEZ0HjkvY5b47_0aJsL8wnHiCyBltXTerUsFza4EtR7tfGkKv5sagQWpvrAd_GxkHmaz8GJd1yT6Ok0W7tojzafXRPgxaLeMToERGC4FeVq4-qITtB-amdP0Y4uztBPwkTMQwzOF47ancwm8g66uI2HRiJ8EI4CAbCQvfcChk1XDANMeMj6dtjv8qwn4gQLXs1iETOcZnxs1NAEg-HJAoGjjCcWMhx1SL89Ydk5eoyYCGLyT-d08_fa_Di5prJa8wLVikWhLxGmVOcvntI59Rse-DhSAv_a046aUV_lzhWqb0F2vXVFHR2kYTQF5t5u0FH1luqShneLauXXWt_BZVyqeyvjX6Hoi94 |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=METHOD+FOR+FABRICATING+A+SEMICONDUCTOR+DEVICE+USING+A+MODELING+ALGORITHM+TO+MODEL+THE+PROXIMITY+EFFECT+FROM+THE+SUB-LAYER&rft.date=2011-02-04&rft.externalDBID=n%2Fa&rft.externalDocID=20120204135 |