7.5 A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture - Yue, Jinshan; Liu, Ruoyang; Sun, Wenyu; Yuan, Zhe; Wang, Zhibo; Tu, Yung-Ning; Chen, Yi-Ju; Ren, Ao; Wang, Yanzhi; Chang, Meng-Fan; Li, Xueqing; Yang, Huazhong; et al. (Digest of technical papers - IEEE International Solid-State Circuits Conference, 2019)
Keywords: Acceleration; Arrays; Artificial neural networks; Biological neural networks; Random access memory; Two dimensional displays