Pipelined cordic architectures for fast VLSI filtering and array processing

The paper presents a revised functional description of Volder's Coordinate Rotation Digital Computer algorithm (CORDIC), as well as allied VLSI implementable processor architectures. Both pipelined and sequential structures are considered. In the general purpose or multi-function case, pipeline...

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Bibliographic Details
Published inICASSP '84. IEEE International Conference on Acoustics, Speech, and Signal Processing Vol. 9; pp. 250 - 253
Main Authors Deprettere, E., Dewilde, P., Udo, R.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1984
Subjects
Algorithm design and analysis
Array signal processing
Circuits
Computer architecture
Filtering
Paper technology
Pipeline processing
Signal processing algorithms
Vectors
Very large scale integration
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DOI10.1109/ICASSP.1984.1172772

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Summary:The paper presents a revised functional description of Volder's Coordinate Rotation Digital Computer algorithm (CORDIC), as well as allied VLSI implementable processor architectures. Both pipelined and sequential structures are considered. In the general purpose or multi-function case, pipeline length (number of cycles), function evaluation time and accuracy are all independent of the various executable functions. High regularity and minimality of data-paths, simplicity of control circuits and enhancement of function evaluation speed are ensured, partly by mapping a unified set of micro-operations, and partly by invoking a natural encoding of the angle parameters. The approach benefits the execution speed in array configurations, since it will allow pipelining at the bit level, thereby providing fast VLSI implementations of certain algorithms exhibiting substantial structural pipelining or parallelism.
DOI:10.1109/ICASSP.1984.1172772