Method for fabricating monolithic and monocrystalline all-semiconductor three-dimensional integrated circuits - WARNER, JR.; RAYMOND M; SCHRIMPF; RONALD D (1998)
A method is described for growing a single crystal having three-dimensional (3-D) doping patterns created within it during growth while maintaining a plane growth surface, creating junction-isolated devices and interconnections, forming a 3-D integrated circuit (IC). The crystal is grown as a large number of lightly-doped layers in a single-pumpdown procedure using sputter epitaxy, which offers growth rates for good-quality silicon of at least 0.1 micrometer per minute. The process experiences a stable environment with temperature remaining around 400 C and pressure near 1 millitorr, and the process is "quasicontinuous" in that once each layer is in place, its surface will experience a short series of further steps that create a 2-D doping pattern extending through the layer. It is the merging of many such successive 2-D patterns that creates the desired 3-D doping pattern within the finished silicon crystal. Primary layer growth is the first step in a five-step process; second is the growth of a thinner secondary layer of heavily doped silicon to serve as a source of dopant; third is exposing the silicon surface to an intense, patterned, focused light flash from an LCD (or silicon mirror) pattern generator, causing localized dopant diffusion through the primary layer; fourth is the uniform removal by ion milling of a layer thicker than the secondary layer, thus eliminating all dopant from the primary layer except in the selected portions of it affected by the light-induced impurity diffusion; and fifth is a uniform flash annealing of the primary layer.