PAGE FAULT PREDICTION FOR PROCESSING VECTOR INSTRUCTIONS - GONION JEFFRY E (2011)
The described embodiments comprise a processor that handles a TLB miss while executing a vector read instruction in a processor. In the described embodiments, the processor performs a lookup in a TLB for addresses in active elements in the vector read instruction. The processor then determines that a TLB miss occurred for the address from an active element other than a first active element. Upon predicting that a page table walk for the vector read instruction will result in a page fault, the processor sets a bit in a corresponding bit position in an FSR. In the described embodiments, a set bit in a bit position in FSR indicates that data in a corresponding element of the vector read instruction is invalid. The processor then immediately performs memory reads for at least one of the first active element and other active elements for which TLB misses did not occur.