SERVICING CPU DEMAND REQUESTS WITH INFLIGHT PREFETCHES - VENKATASUBRAMANIAN, Ramakrishnan; OLORODE, Oluleye (2020)
An instruction request that is a miss in the cache may occur while the cache system is servicing a pending prefetch for the same instruction. Conventionally, a particular cache hazard is detected by comparing request addresses for all entries in a scoreboard. A program memory controller stores the allocated way in the scoreboard. The program memory controller compares (2305) the allocated way of the demand request to the allocated way of all the scoreboard entries. The cache hazard only occurs when the allocated ways match (2306). Following the way compare (2305, 2306), the demand request address is compared (2308) to the request addresses of only those scoreboard entries having matching ways. Other address comparators are not powered during this time. This serves to reduce the electrical power required in detecting this cache hazard.