Meta-Heuristic Optimization of Transistor Sizing in CMOS Digital Designs
Saved in:
| Published in | Proceedings of the 15th International Joint Conference on Computational Intelligence |
|---|---|
| Format | Conference Proceeding |
| Language | English |
| Online Access | Get full text |
| DOI | 10.5220/0012198400003595 |
Cover
| BookMark | eNpdj7FOwzAURT3AUAp7R_9AwH62Y2dEKRCkVhla5ug1caInpU4Up0Lt11MEU89yhyNd6TywuzAEz9hKimcDIF6EkCAzp8UVZTKzYMXWz5gU_jRRnKnm5TjTkS440xD40PL9hCFe1TDxHV0odJwCz7fljq-poxl7vvaRuhAf2X2LffRP_7tkX-9v-7xINuXHZ_66SaKUYBJEwFTKNrUpWgOmcVopdwBtrE4dSpchgGrAoqkPLbapq5Xy2tZOO9DQqCWTf7-nMOL5G_u-Gic64nSupKh-K6vbSvUDGdZK1w |
|---|---|
| ContentType | Conference Proceeding |
| DBID | ADTOC UNPAY |
| DOI | 10.5220/0012198400003595 |
| DatabaseName | Unpaywall for CDI: Periodical Content Unpaywall |
| Database_xml | – sequence: 1 dbid: UNPAY name: Unpaywall url: https://proxy.k.utb.cz/login?url=https://unpaywall.org/ sourceTypes: Open Access Repository |
| DeliveryMethod | fulltext_linktorsrc |
| ExternalDocumentID | 10.5220/0012198400003595 |
| GroupedDBID | ADTOC UNPAY |
| ID | FETCH-LOGICAL-s1125-aa2a611f676a7525d84338b2457468a189a223d27a5cbfaf68c33e47c848242d3 |
| IEDL.DBID | UNPAY |
| IngestDate | Thu Aug 28 11:13:17 EDT 2025 |
| IsDoiOpenAccess | true |
| IsOpenAccess | true |
| IsPeerReviewed | false |
| IsScholarly | false |
| Language | English |
| License | cc-by-nc-nd |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-s1125-aa2a611f676a7525d84338b2457468a189a223d27a5cbfaf68c33e47c848242d3 |
| OpenAccessLink | https://proxy.k.utb.cz/login?url=https://doi.org/10.5220/0012198400003595 |
| ParticipantIDs | unpaywall_primary_10_5220_0012198400003595 |
| PublicationTitle | Proceedings of the 15th International Joint Conference on Computational Intelligence |
| Score | 1.8208485 |
| SourceID | unpaywall |
| SourceType | Open Access Repository |
| Title | Meta-Heuristic Optimization of Transistor Sizing in CMOS Digital Designs |
| URI | https://doi.org/10.5220/0012198400003595 |
| UnpaywallVersion | publishedVersion |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LSwMxEA7aHsSLihUVlRw8CSndvDZ7lNayCH1ALdRTmd0kUqzb0u4i9tebfVBL8aD3SQgTyDdfZuYbhO5BamCBapGAWkG4QxQSWC1IoFtArSdiDYXaZ1-GY_48EZPqvyPvhdnJ37vIwDH2XHMscCykyHkF4hDVpXBRdw3Vx_3h42uZefzV9BgdZckSvj5hPt_BjO5JKWC0LqQG81KR92aWRs14syfE-JfjnKLGT2ceHm4x5wwdmOQchT2TAglNVqou44F7Bj6q_kq8sLjAo0IOBI9mG7cOzxLc7g1GuDN7y4eG4E5Rx7FuoHH36aUdkmpCAlm7OEkQAArS86z0JfiCCq24o5wR5cLnUoGnAnDwr6kPIo4sWKlixgz3Y8WVw2bNLlAtWSTmEmFPMwEMmPAUcEYBhHW7swjAqDj22RV62HpzuiyVMKaOQeRume675fo_xjeolq4yc-vAPY3uqnv9Bg0pnvg |
| linkProvider | Unpaywall |
| linkToUnpaywall | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LSwMxEA7aHsSLihUVlRw8CSndvDZ7lNayCH1ALdRTmd0kUqzb0u4i9tebfVBL8aD3SQgTyDdfZuYbhO5BamCBapGAWkG4QxQSWC1IoFtArSdiDYXaZ1-GY_48EZPqvyPvhdnJ37vIwDH2XHMscCykyHkF4hDVpXBRdw3Vx_3h42uZefzV9BgdZckSvj5hPt_BjO5JKWC0LqQG81KR92aWRs14syfE-JfjnKLGT2ceHm4x5wwdmOQchT2TAglNVqou44F7Bj6q_kq8sLjAo0IOBI9mG7cOzxLc7g1GuDN7y4eG4E5Rx7FuoHH36aUdkmpCAlm7OEkQAArS86z0JfiCCq24o5wR5cLnUoGnAnDwr6kPIo4sWKlixgz3Y8WVw2bNLlAtWSTmEmFPMwEMmPAUcEYBhHW7swjAqDj22RV62HpzuiyVMKaOQeRume675fo_xjeolq4yc-vAPY3uqnv9Bg0pnvg |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=Proceedings+of+the+15th+International+Joint+Conference+on+Computational+Intelligence&rft.atitle=Meta-Heuristic+Optimization+of+Transistor+Sizing+in+CMOS+Digital+Designs&rft_id=info:doi/10.5220%2F0012198400003595&rft.externalDocID=10.5220%2F0012198400003595 |