Meta-Heuristic Optimization of Transistor Sizing in CMOS Digital Designs. Proceedings of the 15th International Joint Conference on Computational Intelligence. https://doi.org/10.5220/0012198400003595
Chicago Style (17th ed.) Citation"Meta-Heuristic Optimization of Transistor Sizing in CMOS Digital Designs." Proceedings of the 15th International Joint Conference on Computational Intelligence . https://doi.org/10.5220/0012198400003595.
MLA (9th ed.) Citation"Meta-Heuristic Optimization of Transistor Sizing in CMOS Digital Designs." Proceedings of the 15th International Joint Conference on Computational Intelligence, , https://doi.org/10.5220/0012198400003595.
Warning: These citations may not always be 100% accurate.