Parallelization of intra prediction algorithm based on array processor

• Published in: 高技术通讯（英文版） Vol. 25; no. 1; pp. 74 - 80
• Main Authors: Zhu Yun, Jiang Lin, Shi Pengfei, Xie Xiaoyan, Shen Xubang
• Format: Journal Article
• Language: English
• Published: School of Microelectronics, Xidian University, Xi'an 710071, P. R. China%Xi'an University of Science and Technology, Xi'an 710054, P. R. China%School of Computer Science and Technology, Xi'an University of Posts and Telecommunications, Xi'an 710121, P. R. China%Xi'an Microelectronic Technology Research Institute, Xi'an 710065, P. R. China 01.03.2019
• Subjects: intra prediction; high-efficiency video coding ( HEVC); parallelization mapping
• ISSN: 1006-6748
• DOI: 10.3772/j.issn.1006-6748.2019.01.010

For the characteristics of intra prediction algorithms, the data dependence and parallelism be-tween intra prediction models are first analyzed. This paper proposes a parallelization method based on dynamic reconfigurable array processors provided by the project team, and uses data level parallel ( DLP) algorithms in multi-core units. The experimental results show that Y-component of peak sig-nal to noise ratio ( Y-PSNR ) is improved about 10 dB and the time is saved 63％ compared with high-efficiency video coding (HEVC) test model HM10. 0. This method can effectively reduce co-dec time of the video and reduce computational complexity.