Enhanced Synaptic Memory Window and Linearity in Planar In2Se3 Ferroelectric Junctions - Jeon, Yu‐Rim; Kim, Dongyoon; Biswas, Chandan; Ignacio, Nicholas D; Carmichael, Patrick; Feng, Shaopeng; Lai, Keji; Kim, Dong‐Hwan; Akinwande, Deji (Advanced materials (Weinheim), 2025)
A synaptic memristor using 2D ferroelectric junctions is a promising candidate for future neuromorphic computing with ultra‐low power consumption, parallel computing, and adaptive scalable computing technologies. However, its utilization is restricted due to the limited operational voltage memory window and low on/off current (ION/OFF) ratio of the memristor devices. Here, it is demonstrated that synaptic operations of 2D In2Se3 ferroelectric junctions in a planar memristor architecture can reach a voltage memory window as high as 16 V (±8 V) and ION/OFF ratio of 108, significantly higher than the current literature values. The power consumption is 10−5 W at the on state, demonstrating low power usage while maintaining a large ION/OFF ratio of 108 compared to other ferroelectric devices. Moreover, the developed ferroelectric junction mimicked synaptic plasticity through pulses in the pre‐synapse. The nonlinearity factors are obtained 1.25 for LTP, −0.25 for LTD, respectively. The single‐layer perceptron (SLP) and convolutional neural network (CNN) on‐chip training results in an accuracy of up to 90%, compared to the 91% in an ideal synapse device. Furthermore, the incorporation of a 3 nm thick SiO2 interface between the α‐In2Se3 and the Au electrode resulted in ultrahigh performance among other 2D ferroelectric junction devices to date. 2D vdW α‐In₂Se₃ is used as a ferroelectric tunneling junction in a planar structure with Au electrodes. The interface between the α‐In₂Se₃ semiconductor and the Au electrode is studied to achieve a large on/off ratio by inserting a SiO₂ insulating barrier. The polarization of α‐In₂Se₃ gradually changes with the applied pulses, mimicking synaptic properties and exhibiting linear LTP/LTD behavior.