AILIS: effective hardware accelerator for incremental learning with intelligent selection in classification

• Published in: The Journal of supercomputing Vol. 81; no. 4; p. 509
• Main Authors: HosseinpourFardi, Nafiseh, Alizadeh, Bijan
• Format: Journal Article
• Language: English
• Published: New York Springer US 17.02.2025; Springer Nature B.V
• Subjects: Accuracy; Algorithms; Artificial intelligence; Classification; Compilers; Computer Science; Datasets; Embedded systems; Feature extraction; Field programmable gate arrays; Hardware; Interpreters; K-nearest neighbors algorithm; Learning; Machine learning; Neural networks; Neurons; Processor Architectures; Programming Languages; K-nearest neighbor methods; Incremental learning; On-chip training; FPGA; AI accelerators
• ISSN: 0920-8542; 1573-0484
• DOI: 10.1007/s11227-025-07017-z

Incremental learning for resource-constrained systems has been noticed for its ability to incorporate new learning. This paper presents accelerator for incremental learning with intelligent selection, a low-latency hardware implementation for incremental learning based on a hardware-modified model. The model consists of two components: (1) feature extractor using convolutional layers (2) classifier based on a customized K-nearest neighbor (KNN) algorithm. We modified classifier to reduce resource usage by utilizing two groups of data: (1) data closest to the class mean for general features (2) boundary data for distinguishing features. The implementation focuses on two strategies: first, simultaneous feature computation for minimal latency, and second, processing features in batches to reduce resource consumption. The first strategy reduced latency by 5 to 912 times compared to previous works. In the second strategy, LUT and DSP usage dropped by 4.8 and 21 times, respectively, and decreased delay was also observed in most cases. Despite these improvements, accuracy remained nearly the same as prior methods.