SEED 암호알고리즘의 Verilog HDL 구현을 위한 최적화 회로구조

• Published in: (사)디지털산업정보학회 논문지, 8(1) Vol. 8; no. 1; pp. 107 - 115
• Main Authors: 이행우, Lee, Haeng Woo
• Format: Journal Article
• Language: Korean
• Published: (사)디지털산업정보학회 01.03.2012
• Subjects: 컴퓨터학; Block Cipher; Verilog HDL; SEED; Cipher Algorithm
• ISSN: 1738-6667; 2713-9018

This paper proposes on the structure for reducing the circuit area and increasing the computation speed in implementing to hardware using the SEED algorithm of a 128-bit block cipher. SEED cipher can be implemented with S/W or H/W method. It should be important that we have minimize the area and computation time in H/W implementation. To increase the computation speed, we used the structure of the pipelined systolic array, and this structure is a simple thing without including any buffer at the input and output circuit. This circuit can record the encryption rate of 320 Mbps at 10 MHz clock. We have designed the circuit with the Verilog HDL coding showing the circuit performances in the figures and the table.