Invited: Enhancing Test Quality by Targeting Timing Marginalities Due to Process Variations

IC test methodologies all generate scan tests based on logical stuck-at and timing fault models that assume only a single passive physical defect localized at some circuit node. However, transistors fabricated in advanced technologies are subject to increasing random process variations that can sign...

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Bibliographic Details
Published in2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 4
Main Authors Singh, Adit D., Faridi, Mukarram Ali
Format Conference Proceeding
LanguageEnglish
Published IEEE 22.06.2025
Subjects
Circuit Simulation
Delays
Digital circuits
Integrated circuit modeling
Integrated circuit reliability
Nonlinear circuits
Path Delay Testing
Performance evaluation
Random processes
Silent Error Corruption
Testing
Threshold voltage
Timing Failures
Transistors
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DOI10.1109/DAC63849.2025.11132918

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Summary:IC test methodologies all generate scan tests based on logical stuck-at and timing fault models that assume only a single passive physical defect localized at some circuit node. However, transistors fabricated in advanced technologies are subject to increasing random process variations that can significantly impact multiple devices, and result in highly nonlinear circuit behavior under specific circuit operating conditions. These changes can cause failures missed by current test methods that mostly target passive defects. We make the case for "variation aware" testing of high-performance digital circuits that prioritizes targeting changes in the most performance sensitive device parameters. Our specific focus in this paper is on developing reliable tests for timing failures caused by random variations in transistor threshold voltages.
DOI:10.1109/DAC63849.2025.11132918