HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design

• Published in: 2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 7
• Main Authors: Luan, Xinya, Lin, Zhe, Shi, Kai, Zhai, Jianwang, Zhao, Kang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 22.06.2025
• Subjects: Field programmable gate arrays; Graphics processing units; Recommender systems; Search problems; Signal processing; Signal processing algorithms; Singular value decomposition; Space exploration; Throughput; Time complexity
• DOI: 10.1109/DAC63849.2025.11132878

Singular value decomposition (SVD) is a matrix factorization technique widely used in signal processing and recommendation systems, etc. In general, the time complexity of SVD algorithms is cubic to the problem size, making SVD algorithms difficult to meet stringent performance requirements in real-time. However, existing FPGA and GPU solutions fall short of jointly optimizing latency, throughput, and power consumption. To settle this issue, this paper proposes HeteroSVD, a heterogeneous reconfigurable accelerator for SVD computation on the Versal ACAP platform. HeteroSVD introduces a system-level SVD decomposition mechanism and proposes an algorithm-hardware co-design method to optimize SVD ordering jointly and AI engine (AIE)-centric dataflow and placement with Versal. Furthermore, in order to improve the quality of results (QoR) and facilitate micro-architecture selection, we introduce an automatic optimization framework that performs accurate performance modeling and fast design space exploration. Experiment results demonstrate that HeteroSVD reduces the latency by 1.98 \times over existing FPGA accelerators and outperforms GPU solutions with an improvement of up to 7.22 \times in latency, 1.77 \times in throughput, and 13.18 \times in energy efficiency.