PV-Clock: Process Variation-Aware 3D Clock Network Synthesis for Robust and Power-Efficient Timing Optimization - Wang, Yiyu; Pavlidis, Vasilis F.; Wang, Rui; Cheng, Yuanqing (Proceedings / IEEE Computer Society Annual Symposium on VLSI, 2025)
Keywords: 3D ICs; Clock Network Synthesis; Clocks; Geometric Optimization; Measurement; Multichip modules; Network synthesis; Optimization; Power demand; Process Variations; Robustness; Three-dimensional displays; Timing; Very large scale integration