A 2-Tap Half-Rate 25Gb/s Adaptive DFE in 55nm CMOS

To address signal integrity degradation in highspeed serial links, this paper presents a 25 \mathrm{~Gb} / \mathrm{s} adaptive decision-feedback equalizer (DFE) implemented in 55 nm CMOS technology. The proposed architecture employs a half-rate 2-tap topology to alleviate critical timing constraints...

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Bibliographic Details
Published in2025 10th International Conference on Electronic Technology and Information Science (ICETIS) pp. 65 - 68
Main Authors Xie, Yisha, Guo, Aiying
Format Conference Proceeding
LanguageEnglish
Published IEEE 27.06.2025
Subjects
Adaptive
Complexity theory
Current-mode logic (CML)
Decision feedback equalizers
Decisionfeedback equalizer (DFE)
Inter-symbol interference (ISI)
Interference
Jitter
Least mean squares algorithm (LMS)
Logic
Main-secondary
Signal integrity
Simulation
Timing
Topology
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DOI10.1109/ICETIS66286.2025.11144164

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Summary:To address signal integrity degradation in highspeed serial links, this paper presents a 25 \mathrm{~Gb} / \mathrm{s} adaptive decision-feedback equalizer (DFE) implemented in 55 nm CMOS technology. The proposed architecture employs a half-rate 2-tap topology to alleviate critical timing constraints in the feedback path, utilizing current-mode logic (CML) circuits for high-speed operation. An analog least mean squares algorithm (LMS) based adaptation engine continuously optimizes tap coefficients, incorporating a LMS algorithm to reduce hardware complexity. The core circuit integrates CML-based current-summing adders and master-slave D-flip-flops (MSDFF) with inductive peaking, while the adaptive module combines a sense amplifier (SA) for error detection and Gilbert-cell multipliers with Gm-C integrators for coefficient updates.
DOI:10.1109/ICETIS66286.2025.11144164