CMOS Analog Artificial Neural Network

• Published in: Devices for Integrated Circuit pp. 433 - 438
• Main Authors: Singh, Jagmeet, Babu, Kondrakunta Prasanth, Harshith, Samala, Tripathi, Suman Lata
• Format: Conference Proceeding
• Language: English
• Published: IEEE 05.04.2025
• Subjects: Analog Neural Networks; Artificial intelligence; Artificial neural networks; Biological neural networks; CMOS technology; Computer architecture; Gilbert Cell Multiplier; Hardware; Low-Power AI Hardware; Microprocessors; Neurons; Power demand; Real-time systems; Sigmoid Activation Function
• ISSN: 2996-3044
• DOI: 10.1109/DevIC63749.2025.11012358

This paper focuses on the design and simulation of low power analog artificial neural network (ANN) using 180nm CMOS technology in Cadence Virtuoso. The neurons here are designed in such a manner that they could perform key biological functions, namely multiplication of the signal, summation, and thresholding. The design exploits advantages of analog computation, leading to lower power dissipation and better processing speed in comparison to purely digital implementations. This makes it particularly suitable for real-time applications. Simulations are performed at different process corners for power consumption analysis to ensure the performance of the network, establishing its efficiency for low-power AI solutions. The key design components include Gilbert cell multipliers for weight multiplication and CMOS-based sigmoid activation functions to provide efficient analog alternatives of the traditional digital elements of a neural network.