On-chip Network Optimization using U-mesh Algorithm - Naik, Yogesh S; P., Deepa N.; Jain, Siddhanth V; Pai, Shashank; Hulakund, Rohit (2024 2nd International Conference on Recent Advances in Information Technology for Sustainable Development (ICRAIS), 2024)
This work presents an approach to optimize the network and reduce the congestion within a chip. It involves using NVIDIA Simba architecture as reference for Processing Element (PE). Increasing complexity within the development of multicore processors increases the need for optimization within Network-on-Chip architectures to achieve high performance in modern computing. This paper also presents the strategies in addressing major issues related to latency, and scalability in NoC systems. It concerns methods like Based Routing Conformed Paths, which improves efficiency in multicasting, the Forward & Absorb multicast method, which resolves deadlock issues related to the interaction between multicast and unicast traffic and the U-mesh algorithm used in the Advanced Hierarchical scheme, which supports efficient cycles and traffic management to further contribute to NoC performance. The proposed system involves using python script, GUI interface to generate Verilog code for the routing table in 2D 4x5 mesh network. The Leaders (L1 & L2) are selected based on U-mesh to route the data. The comparative analysis between the two algorithms are conducted and the simulation waveforms are shown. This paper explores a wide spectrum of technologies like semiconductor technology to high performance computing and consumer electronics, in general with implications for aerospace, space and defense applications.