A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS

Streaming scan test architectures can greatly optimize the test data delivery to large industrial designs. This paper discusses what happens when such architectures are combined with nearly unlimited data bandwidth provided by NVIDIA MATHS (Mechanism to Access Test-Data over High-Speed Link). There...

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Bibliographic Details
Published inProceedings - International Test Conference pp. 400 - 406
Main Authors Mangilal, Kunal Jain, Yilmaz, Mahmut, Agarwal, Vishal, Sarangi, Shantanu, Narayanun, Kaushik
Format Conference Proceeding
LanguageEnglish
Published IEEE 03.11.2024
Subjects
Bandwidth
concurrent testing
Costs
high-speed interface
PCIE
scan architecture
Silicon
SoC Test
Streaming Scan
test access mechanism
test time
Throughput
Online AccessGet full text
ISSN2378-2250
DOI10.1109/ITC51657.2024.00062

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Summary:Streaming scan test architectures can greatly optimize the test data delivery to large industrial designs. This paper discusses what happens when such architectures are combined with nearly unlimited data bandwidth provided by NVIDIA MATHS (Mechanism to Access Test-Data over High-Speed Link). There are multiple techniques for efficient use of scan bandwidth and its impact on the overall test cost and test quality. We have also architected various debug techniques for silicon bring-up. This scan architecture was designed for highest throughput to test multiple dies in parallel with lowest test power and best diagnosability.
ISSN:2378-2250
DOI:10.1109/ITC51657.2024.00062