CORDIC Based Implementation of QPSK Modulator Using FPGA

• Published in: International Conference on Computing, Communication, and Networking Technologies (Online) pp. 1 - 7
• Main Author: Al-Safi, Amean
• Format: Conference Proceeding
• Language: English
• Published: IEEE 24.06.2024
• Subjects: CORDIC; Costs; DDS; Digital Modulators; Field programmable gate arrays; FPGA; Generators; Hardware; Industries; QPSK Modulator; Quadrature phase shift keying; Radio frequency; System-on-chip; Very high speed integrated circuits; VHDL
• ISSN: 2473-7674
• DOI: 10.1109/ICCCNT61001.2024.10724933

Digital modulators have received great attention recently due to the tremendous progress in Radio Frequency (RF) front end terminals and system on chip industry. But with all the progress that has been made, the implementation cost still a challenge. This paper presents a new method of implementing Quadrature Phase Shift Keying (QPSK) modulator in VHDL at the lowest possible implementation cost. Four different carrier signals were generated using CORDIC(COordinate Rotation DIgital Computer) algorithm. Two phase accumulators are included within the CORDIC processor to yield four sinusoidal carriers. The first accumulator has a zero starting phase, whereas the second one has a 180-degree phase shift compared with the first one. The whole implementation process was done directly in Very high speed integrated circuit Hardware Descriptive Language (VHDL) using XILINX Vivado without the help of any co-simulation tool such as Xilinx System Generator or DSP Builder Tools as in many papers. The implemented modulator uses 48 slice LUT,32 FF(Flip Flop), 9 input/output peripherals, and one buffer only.