A Novel Flash Fast-Locking Digital PLL: VHDL-AMS and Matlab/Simulink Modeling and Simulations

A novel flash fast-locking digital phase-locked loop (DPLL) is presented and behaviorally modeled. The DPLL operation includes two stages: (1) a novel coarse-tuning stage for frequency tracking which employs a flash algorithm similar to the one employed in flash A/D converters (ADCs) and (2) a fine-...

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Bibliographic Details
Published in2011 Eighth International Conference on Information Technology: New Generations pp. 777 - 784
Main Authors Wagdy, M. F., Nannaka, A., Channegowda, R. K. N.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2011
Subjects
Arrays
behavioral modeling
coarse tuning
DPLL
fast-locking
fine tuning
flash algorithm
Frequency conversion
frequency tracking
lock time
MATLAB
Phase frequency detector
Phase locked loops
phase tracking
PLL
SIMULINK
Time frequency analysis
Tuning
VHDL-AMS
Voltage-controlled oscillators
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ISBN9781612844275
1612844278
DOI10.1109/ITNG.2011.136

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Summary:A novel flash fast-locking digital phase-locked loop (DPLL) is presented and behaviorally modeled. The DPLL operation includes two stages: (1) a novel coarse-tuning stage for frequency tracking which employs a flash algorithm similar to the one employed in flash A/D converters (ADCs) and (2) a fine-tuning stage similar to conventional (classical) DPLLs. The coarse-tuning stage includes an array of frequency comparators, a priority encoder, a digital-to-analog converter (DAC), and control logic. Design considerations and implementations are presented in this paper. VHDL-AMS (Simplorer) and Matlab/Simulink are used to design and perform simulations. The fast-locking DPLL reduces the lock time by a factor of about 1.80 compared to its conventional DPLL counterpart.
ISBN:9781612844275
1612844278
DOI:10.1109/ITNG.2011.136