APA (7th ed.) Citation

Zoellin, C. G., & Wunderlich, H. (2010, April). Low-power test planning for arbitrary at-speed delay-test clock schemes. 2010 28th VLSI Test Symposium (VTS), 93-98. https://doi.org/10.1109/VTS.2010.5469607

Chicago Style (17th ed.) Citation

Zoellin, Christian G., and Hans-Joachim Wunderlich. "Low-power Test Planning for Arbitrary At-speed Delay-test Clock Schemes." 2010 28th VLSI Test Symposium (VTS) Apr. 2010: 93-98. https://doi.org/10.1109/VTS.2010.5469607.

MLA (9th ed.) Citation

Zoellin, Christian G., and Hans-Joachim Wunderlich. "Low-power Test Planning for Arbitrary At-speed Delay-test Clock Schemes." 2010 28th VLSI Test Symposium (VTS), Apr. 2010, pp. 93-98, https://doi.org/10.1109/VTS.2010.5469607.